Timing Gets Worse After Inserting MBIST

Before the MBIST (Memory Build-in Self Test) function was inserted in RTL, I had got a quite good timing result of TD-modem. The violation on critical path was less than 0.3 ns. Now the synthesis timing gets much too worse after adding MBIST logic. I got more than 2.0 ns violations. Oops...

So it is much possible for designers to change the RTL to fix the timing violations next week. Such fixing will not be a easy job. But I have to ask them finish it in two days, because the tap-out schedule (2.24) is too close.